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MSPM0G1519

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80 MHz ARM® Cortex®-M0+ MCU with dual-bank 512kB flash, 128kB SRAM, 2xADC, DAC, 3xCOMP

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MSPM0G1519

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Data sheet Order now

Product details

Frequency (MHz) 80 Flash memory (kByte) 512 RAM (kByte) 128 ADC type 12-bit SAR Number of ADC channels 15, 19, 27 Number of GPIOs 28, 44, 60, 74, 94 UART 7 Number of I2Cs 3 SPI 3 Features 5-V-tolerant I/Os, AES encryption, Comparator, DAC, DMA, MATHACL, RTC Operating temperature range (°C) -40 to 125 Rating Catalog
Frequency (MHz) 80 Flash memory (kByte) 512 RAM (kByte) 128 ADC type 12-bit SAR Number of ADC channels 15, 19, 27 Number of GPIOs 28, 44, 60, 74, 94 UART 7 Number of I2Cs 3 SPI 3 Features 5-V-tolerant I/Os, AES encryption, Comparator, DAC, DMA, MATHACL, RTC Operating temperature range (°C) -40 to 125 Rating Catalog
VQFN (RGZ) 48 49 mm² 7 x 7 VQFN (RHB) 32 25 mm² 5 x 5
  • Core
    • Arm 32-bit Cortex M0+ CPU with memory protection unit, frequency up to 80MHz
  • Functional Safety-Compliant targeted

    • Developed for functional safety applications

    • Functional Safety Manual and FMEDA available to aid in functional safety system design

    • Systematic capability up to ASIL B targeted

  • Operating characteristics
    • Extended temperature: –40°C up to 125°C
    • Wide supply voltage range: 1.62V to 3.6V
  • Memories
    • Up to 512KB of flash memory with error correction code (ECC)

      • Dual-bank with address swap for OTA updates

    • 16KB data flash bank with ECC protection
    • 128KB total SRAM
      • SRAM (Bank 0): 64kB SRAM with ECC protection or hardware parity, and retention down to STANDBY mode
      • SRAM (Bank 1) : 64kB SRAM with retention down to SLEEP mode
  • High-performance analog peripherals
    • Two simultaneous sampling 12-bit 4Msps analog-to-digital converters (ADCs) with up to 27 external channels
      • 14-bit effective resolution at 250ksps with hardware averaging
    • One 12-bit 1-MSPS digital-to-analog converter with integrated output buffer (DAC)
    • Three high-speed comparators (COMP) with integrated 8-bit reference DACs
      • 32ns propagation delay in high-speed mode
      • Support low-power mode operation down to <1µA
    • Programmable analog connections between ADC, COMP and DAC
    • Configurable 1.4V or 2.5V internal shared voltage reference (VREF)
    • Integrated temperature sensor
  • Optimized low-power modes
    • RUN: 121µA/MHz (CoreMark)
    • SLEEP: 614µA at 4MHz
    • STOP: 56µA at 32 kHz
    • STANDBY: 1.7µA with RTC and SRAM retention
    • SHUTDOWN: 93nA with IO wake-up capability
  • Intelligent digital peripherals
    • 12-channel DMA controller
    • Math accelerator supports DIV, SQRT, MAC and TRIG computations
    • Nine timers support up to 28 PWM channels
      • Three 16-bit general-purpose timers
      • Two 16-bit general-purpose timers support QEI
      • One 16-bit general-purpose timer support low-power operation in STANDBY mode
      • One 32-bit high-resolution general-purpose timer
      • Two 16-bit advanced timers with deadband support and complimentary outputs up to 12 PWM channels
    • Two windowed watchdog timers (WWDT), one independent watchdog timer (IWDT)
    • RTC with alarm and calendar mode
  • Enhanced communication interfaces
    • Seven UART interfaces
      • Two supporting LIN, IrDA, DALI, Smart Card, Manchester
      • Five basic instances, including one supporting low-power operation in STANDBY mode
    • Three I2C interfaces supporting up to FM+ (1Mbit/s), SMBus/PMBus, and wakeup from STOP mode
    • Three SPIs supports up to 32Mbits/s
    • Two Controller Area Network (CAN) interfaces support CAN 2.0 A or B and CAN-FD
  • Clock system
    • Internal 4 to 32MHz oscillator with up to ±1.2% accuracy (SYSOSC)
    • Phase-locked loop (PLL) up to 80MHz
    • Internal 32kHz low-frequency oscillator (LFOSC) with ±3% accuracy
    • External 4 to 48MHz crystal oscillator (HFXT)
    • External 32kHz crystal oscillator(LFXT)
    • External clock input
  • Data integrity and encryption
    • AES-128/256 accelerator with support for GCM/GMAC, CCM/CBC-MAC, CBC, CTR
    • Secure Key Storage for up to four AES keys
    • Flexible firewalls for protecting code and data
    • True random number generator (TRNG)
    • Cyclic redundancy checker (CRC-16, CRC-32)
    • Extensive security features
  • Flexible I/O features
    • Up to 94 GPIOs
      • Two 5V-tolerant open-drain IOs
      • Three high-drive IOs with 20mA drive strength

      • Four high-speed IOs

  • Development support
    • 2-pin serial wire debug (SWD)
  • Package options
    • 100-pin LQFP (0.5mm pitch)

    • 80-pin LQFP (0.5mm pitch)

    • 64-pin LQFP (0.5mm pitch)

    • 48-pin LQFP (0.5mm pitch)

    • 48-pin VQFN (0.5mm pitch)

    • 32-pin VQFN (0.5mm pitch)

  • Family members (also see Device Comparison)
    • MSPM0G3519: 512KB flash, 128KB RAM
    • MSPM0G3518: 256KB flash, 128KB RAM
    • MSPM0G1519: 512KB flash, 128KB RAM
    • MSPM0G1518: 256KB flash, 128KB RAM
  • Development kits and software (also see Tools and Software)
  • Core
    • Arm 32-bit Cortex M0+ CPU with memory protection unit, frequency up to 80MHz
  • Functional Safety-Compliant targeted

    • Developed for functional safety applications

    • Functional Safety Manual and FMEDA available to aid in functional safety system design

    • Systematic capability up to ASIL B targeted

  • Operating characteristics
    • Extended temperature: –40°C up to 125°C
    • Wide supply voltage range: 1.62V to 3.6V
  • Memories
    • Up to 512KB of flash memory with error correction code (ECC)

      • Dual-bank with address swap for OTA updates

    • 16KB data flash bank with ECC protection
    • 128KB total SRAM
      • SRAM (Bank 0): 64kB SRAM with ECC protection or hardware parity, and retention down to STANDBY mode
      • SRAM (Bank 1) : 64kB SRAM with retention down to SLEEP mode
  • High-performance analog peripherals
    • Two simultaneous sampling 12-bit 4Msps analog-to-digital converters (ADCs) with up to 27 external channels
      • 14-bit effective resolution at 250ksps with hardware averaging
    • One 12-bit 1-MSPS digital-to-analog converter with integrated output buffer (DAC)
    • Three high-speed comparators (COMP) with integrated 8-bit reference DACs
      • 32ns propagation delay in high-speed mode
      • Support low-power mode operation down to <1µA
    • Programmable analog connections between ADC, COMP and DAC
    • Configurable 1.4V or 2.5V internal shared voltage reference (VREF)
    • Integrated temperature sensor
  • Optimized low-power modes
    • RUN: 121µA/MHz (CoreMark)
    • SLEEP: 614µA at 4MHz
    • STOP: 56µA at 32 kHz
    • STANDBY: 1.7µA with RTC and SRAM retention
    • SHUTDOWN: 93nA with IO wake-up capability
  • Intelligent digital peripherals
    • 12-channel DMA controller
    • Math accelerator supports DIV, SQRT, MAC and TRIG computations
    • Nine timers support up to 28 PWM channels
      • Three 16-bit general-purpose timers
      • Two 16-bit general-purpose timers support QEI
      • One 16-bit general-purpose timer support low-power operation in STANDBY mode
      • One 32-bit high-resolution general-purpose timer
      • Two 16-bit advanced timers with deadband support and complimentary outputs up to 12 PWM channels
    • Two windowed watchdog timers (WWDT), one independent watchdog timer (IWDT)
    • RTC with alarm and calendar mode
  • Enhanced communication interfaces
    • Seven UART interfaces
      • Two supporting LIN, IrDA, DALI, Smart Card, Manchester
      • Five basic instances, including one supporting low-power operation in STANDBY mode
    • Three I2C interfaces supporting up to FM+ (1Mbit/s), SMBus/PMBus, and wakeup from STOP mode
    • Three SPIs supports up to 32Mbits/s
    • Two Controller Area Network (CAN) interfaces support CAN 2.0 A or B and CAN-FD
  • Clock system
    • Internal 4 to 32MHz oscillator with up to ±1.2% accuracy (SYSOSC)
    • Phase-locked loop (PLL) up to 80MHz
    • Internal 32kHz low-frequency oscillator (LFOSC) with ±3% accuracy
    • External 4 to 48MHz crystal oscillator (HFXT)
    • External 32kHz crystal oscillator(LFXT)
    • External clock input
  • Data integrity and encryption
    • AES-128/256 accelerator with support for GCM/GMAC, CCM/CBC-MAC, CBC, CTR
    • Secure Key Storage for up to four AES keys
    • Flexible firewalls for protecting code and data
    • True random number generator (TRNG)
    • Cyclic redundancy checker (CRC-16, CRC-32)
    • Extensive security features
  • Flexible I/O features
    • Up to 94 GPIOs
      • Two 5V-tolerant open-drain IOs
      • Three high-drive IOs with 20mA drive strength

      • Four high-speed IOs

  • Development support
    • 2-pin serial wire debug (SWD)
  • Package options
    • 100-pin LQFP (0.5mm pitch)

    • 80-pin LQFP (0.5mm pitch)

    • 64-pin LQFP (0.5mm pitch)

    • 48-pin LQFP (0.5mm pitch)

    • 48-pin VQFN (0.5mm pitch)

    • 32-pin VQFN (0.5mm pitch)

  • Family members (also see Device Comparison)
    • MSPM0G3519: 512KB flash, 128KB RAM
    • MSPM0G3518: 256KB flash, 128KB RAM
    • MSPM0G1519: 512KB flash, 128KB RAM
    • MSPM0G1518: 256KB flash, 128KB RAM
  • Development kits and software (also see Tools and Software)

MSPM0Gx51x microcontrollers (MCUs) are part of the MSP highly integrated, ultra-low-power 32-bit MCU family based on the enhanced Arm Cortex-M0+ 32-bit core platform, operating at up to 80MHz frequency. These MCUs offer a blend of cost optimization and design flexibility for applications requiring 256KB to 512KB of flash memory in small packages (down to 5mm x 5mm) or high pin count packages (up to 100 pins). These devices include dual CAN-FD controllers, cybersecurity enablers, high performance integrated analog, and provide excellent low power performance across the operating temperature range.

Up to 512KB of embedded flash program memory with built-in error correction code (ECC) and up to 128KB SRAM (with ECC and parity protection for the first 64kB). The flash memory is organized into two main banks to support field firmware updates, with address swap support provided between the two main banks.

Flexible cybersecurity enablers can be used to support secure boot, secure in-field firmware updates, IP protection (execute-only memory), key storage, and more. Hardware acceleration is provided for a variety of AES symmetric cipher modes, as well as a TRNG entropy source. The cybersecurity architecture is pending Arm® PSA Level 1 certification.

A set of high performance analog modules is provided, such as two simultaneously sampling 12-bit 4Msps ADCs supporting up to 27 external channels, on-chip voltage reference (1.4V or 2.5V), one 12-bit 1Msps DAC, and three high speed comparators with built-in 8-bit reference DACs operable in low-power and high-speed modes.

The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital integration allowing for customers find the MCU that meets their project’s needs. The MSPM0 MCU platform combines the Arm Cortex-M0+ platform with a holistic ultra-low-power system architecture, allowing system designers to increase performance while reducing energy consumption.

MSPM0Gx51x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get the design started quickly. Development kits include a LaunchPad available for purchase. TI also provides a free MSPM0 Software Development Kit (SDK), which is available as a component of Code Composer Studio™ IDE desktop and cloud version within the TI Resource Explorer. MSPM0 MCUs are also supported by extensive online collateral, training with MSP Academy, and online support through the TI E2E™ support forums.

For complete module descriptions, see the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual.

MSPM0Gx51x microcontrollers (MCUs) are part of the MSP highly integrated, ultra-low-power 32-bit MCU family based on the enhanced Arm Cortex-M0+ 32-bit core platform, operating at up to 80MHz frequency. These MCUs offer a blend of cost optimization and design flexibility for applications requiring 256KB to 512KB of flash memory in small packages (down to 5mm x 5mm) or high pin count packages (up to 100 pins). These devices include dual CAN-FD controllers, cybersecurity enablers, high performance integrated analog, and provide excellent low power performance across the operating temperature range.

Up to 512KB of embedded flash program memory with built-in error correction code (ECC) and up to 128KB SRAM (with ECC and parity protection for the first 64kB). The flash memory is organized into two main banks to support field firmware updates, with address swap support provided between the two main banks.

Flexible cybersecurity enablers can be used to support secure boot, secure in-field firmware updates, IP protection (execute-only memory), key storage, and more. Hardware acceleration is provided for a variety of AES symmetric cipher modes, as well as a TRNG entropy source. The cybersecurity architecture is pending Arm® PSA Level 1 certification.

A set of high performance analog modules is provided, such as two simultaneously sampling 12-bit 4Msps ADCs supporting up to 27 external channels, on-chip voltage reference (1.4V or 2.5V), one 12-bit 1Msps DAC, and three high speed comparators with built-in 8-bit reference DACs operable in low-power and high-speed modes.

The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital integration allowing for customers find the MCU that meets their project’s needs. The MSPM0 MCU platform combines the Arm Cortex-M0+ platform with a holistic ultra-low-power system architecture, allowing system designers to increase performance while reducing energy consumption.

MSPM0Gx51x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get the design started quickly. Development kits include a LaunchPad available for purchase. TI also provides a free MSPM0 Software Development Kit (SDK), which is available as a component of Code Composer Studio™ IDE desktop and cloud version within the TI Resource Explorer. MSPM0 MCUs are also supported by extensive online collateral, training with MSP Academy, and online support through the TI E2E™ support forums.

For complete module descriptions, see the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual.
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Technical documentation

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Type Title Date
* Data sheet MSPM0Gx51x Mixed-Signal Microcontrollers With CAN-FD Interface datasheet PDF | HTML 01 Nov 2024
* User guide MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual (Rev. B) PDF | HTML 12 Nov 2024
Application note MSPM0G3507 Low Power Test and Guidance PDF | HTML 18 Oct 2024
Application note MSPM0 Design Flow Guide (Rev. D) PDF | HTML 16 Oct 2024
Application note MSPM0 ADC Noise Analysis and Application PDF | HTML 15 Oct 2024
Application note Understanding the MSPM0 Debug Subsystem PDF | HTML 23 Sep 2024
Subsystem design Frequency Counter: Tone Detection PDF | HTML 05 Sep 2024
Application note Migration Guide From STM8 to MSPM0 PDF | HTML 06 Dec 2023
Application note Operating Time of MSPM0 Powered by a Capacitor PDF | HTML 03 Oct 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LP-MSPM0G3519 — MSPM0G3519 LaunchPad™ development kit for 80MHz Arm® Cortex®-M0+ MCU

The LP-MSPM0G3519 LaunchPad™ development kit is an easy-to-use evaluation module (EVM) based on the MSPM0G3519. It contains everything needed to start developing on the MSPM0G3519 M0+ MCU platform, including on-board debug probe for programming, debugging and energy measurements. The board includes (...)

User guide: PDF | HTML
Not available on TI.com
Driver or library

MSPM0-DIAGNOSTIC-LIB — MSPM0 diagnostic library for functional safety applications

The MSPM0 diagnostic library software development kit (SDK) is a collection of functional safety software to assist customers to meet their functional safety diagnostic requirements.
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VQFN (RGZ) 48 Ultra Librarian
VQFN (RHB) 32 Ultra Librarian
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